After the course, students will be able to explain that the hardware works in parallel and to exploit parallelism in VHDL, explain the function, use, and limitations of reconfigurable versus ASIC technologies, describe a digital design in VHDL, perform simulation and synthesis with modern tools and perform tests against the target technology, create the design specifications of a digital circuit for a given problem apply structured methods for analysis and synthesis of combinational and sequential circuits, use VHDL to implement combinatorial and sequential circuits, use the target FPGA technology to implement a digital hardware design, define FSM encodings and perform state minimization, be able to implement FSMs in VHDL and understand their timing properties, create test benches for VHDL designs, describe and perform the steps required from the VHDL description of a hardware module to its synthesis and hardware implementation.
The aims of this course are:
Upon completion of this course, the students could:
Textbook:
References:
Evaluation | Marks | Percentage |
---|---|---|
Tutorial/Discussion | 10 Marks | 10% |
Assignments | 10 Marks | 10% |
Project | 20 Marks | 20% |
Final Examination | 60 Marks | 60% |